U.S. Pat. No. 5,737,340, U.S. Pat. No. 6,681,359 B1, U.S. Pat. No. 6,070,261, U.S. Pat. No. 5,737,340, U.S. Pat. No. 5,991,909, U.S. Pat. No. 5,991,898, U.S. Pat. No. 6,625,769, U.S. Pat. No. 6,738,938 B2 and U.S. Pat. No. 5,995,731 disclose built-in self-test (BIST) apparatus and methods for testing integrated circuits which enable various methods for capturing failure data for a selected failure. A BIST apparatus includes a clock generator which generates a clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. The BIST apparatus further includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus also includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.
This prior art suggests that the method can be used to capture all failure data of a memory by iteratively applying the method. However, collecting information in this manner can be extremely time consuming.
For these and other reasons, there is a need for the present invention.